1. Field of the Invention
The present invention relates to a packet transmission apparatus, and more particularly to a packet transmission apparatus achieving high-speed processing capability and enhanced relay quality for multicast relay packets. The use of such packets has been rapidly increasing with the widespread use of the Internet in recent years.
2. Description of the Related Art
With the improvements that have been made in the packet processing capabilities of packet transmission apparatuses in recent years, transmission of packets having longer packet lengths than before has become possible. On the other hand, to achieve efficient packet transmission, the transmission speed of packets from the packet transmission apparatus must be matched to that of the transmission line over which the packets are transmitted.
For this purpose, it has been practiced to transmit relay packets at predetermined intervals or control packet transmission spacing by measuring relay packets over a long span, in order to achieve improvements in the packet processing capability and relay quality of the packet transmission apparatus. The packet transmission speed here refers to the number of bits of packets transmitted per second (bps).
In the case of fixed-length packets, efficient packet transmission can be achieved by determining the packet spacing according to the packet length and line speed, because the transmission speed can be maintained constantly at a value close to the line speed even if the packets are transmitted at predetermined intervals.
However, in the case of variable-length packets, as the packet transmission speed (the number of bits of packets transmitted per second) of the packet transmission apparatus varies depending on the packet length, there has been the problem that the difference between the line speed and the transmission speed becomes large, degrading the packet relay performance of the packet transmission apparatus as well as the packet relay quality. Furthermore, when controlling the packet transmission spacing to match the line speed by measuring the transmitted packets, circuitry having a function equivalent to that of a conventional transmit request unit becomes necessary, resulting in the problem that the amount of circuitry increases correspondingly.
FIG. 1 is a diagram showing examples of packet transmission spacing control in a packet transmission apparatus.
In FIG. 1, it is assumed that the packet transmission apparatus has a packet data bus speed of 12.8 Gbps (bus clock of 100 MHz, bus width of 128 bits), and that the line speed is 1 Gbps. Examples 1 and 2 show examples of transmission spacing control for fixed-length packets, and examples 3 to 5 concern examples of transmission spacing control for variable-length packets.
Example 1 shows the case in which 54-byte fixed-length packets are transmitted with no spacing in between (packet spacing “0”); in this case, the packet transmission speed is 12.8 Gbps and far exceeds the line speed of 1 Gbps. Therefore, in example 2, in order to match the packet transmission speed to the line speed, the packet transmission spacing is controlled to 40 clocks, thereby achieving a packet transmission speed of 0.98 Gbps which is close to the line speed.
In example 3, 1500-byte variable-length packets are transmitted with the packet transmission spacing of 40 clocks; in this case, the packet transmission speed is 8.9 Gbps and far exceeds the line speed. Therefore, in example 4, the packet transmission spacing for 1500-byte variable-length packets is increased to 1100 clocks to make the packet transmission speed match the line speed of 1 Gbps. In this case, if 54-byte variable-length packets are transmitted with the spacing of 1100 clocks, as shown in example 5, the packet transmission speed is 0.04 Gbps falling far short of the line speed.
In this way, packet transmission spacing control for variable-length packets is difficult compared with that for fixed-length packets, the former having the problem that if the packet transmission speed exceeds the line speed, some of the transmit packets will be discarded at the line interface, etc. of the packet transmission apparatus, resulting in degradation of packet relay quality, and conversely, if the packet transmission speed is slower than the line speed, this will also degrade the packet relay quality.
FIG. 2 is a diagram showing one example of multicast packet processing in a prior art packet transmission apparatus.
In the packet transmission apparatus, arbitration for an outgoing channel (outgoing port), the order of transmission, etc. is done among a plurality of packets to be transmitted. It is assumed here that packet A is a multicast packet that has a plurality of destinations and whose copies are transmitted to channel 0. It is also assumed that packet B is an ordinary packet, with no copies, that has one destination and is transmitted to channel 1.
As the result of arbitration, in the illustrated example, first the packet A is transmitted out for channel 0, and then the packet B is transmitted out for channel 1. In this case, the packet B for channel 1 is transmitted out after all the copies of the packet A have been transmitted out. This means that during the time that the copy packets for channel 0 are being transmitted out preferentially, the packet for channel 1 cannot be transmitted.
Since the presence or absence of copy packets to be transmitted is not considered in determining the packet transmission order, the prior art arbitration has had the problem that packet relay to a particular channel is interrupted for a finite period, as described above. Therefore, in a network where such preferential transmission of copy packets is not desired, the problem has been that relay line quality for a particular channel degrades because of transmission of such copy packets.
Furthermore, since, in the prior art, the transmit request unit simply performs packet transmission spacing control on a particular destination channel or between destination channels, the prior art has had the problem that when copy packets occur for one outgoing port, the transmission spacing of the copy packets cannot be controlled.
FIG. 3 is a diagram showing one example of packet add/delete operations in a prior art packet transmission apparatus.
As shown in FIG. 3, in the prior art, the bit width of the packet data bus is 32 bits, and the addition or deletion of a packet is also performed in units of 32 bits. As a result, the addition of a new packet (DN) can be accomplished by just reading the same address data (D3) on a 32-bit wide FIFO twice, and similarly, the deletion of a packet can be accomplished by skipping the reading of particular address data (D3) and thereby deleting the designated address area.
In this way, in the prior art, since the bit width of the packet bus is small, and since the minimum area that needs packet addition or deletion is not divided into smaller areas, it has been possible to readily add or delete the designated area by just controlling the FIFO address. However, with increasing processing speeds in recent years, the bit width of the packet bus has been increasing beyond 32 bits, and besides, there is a tendency that the add/delete area is divided into smaller areas, for example, 16 bits wide; this has given rise to the problem that, with the prior art simple processing method, it is difficult to add or delete packets.